1. Field of the Invention
The present invention relates to a semiconductor chip packaging technology. More particularly, the present invention relates to a method of forming a stack package and structure thereof.
2. Description of the Related Art
In recent years, the technology developments and the popularity of portable, handheld and consumer electronic products has almost overshadowed the conventional personal computer (PC) products. To facilitate the manufacturing of these electronic products, most devices are designed towards higher storage capacity and smaller line width to increase the packing density, the operational frequency, to reduce the power consumption and to achieve the integration of multi-functions. In the packaging technology of the integrated circuits (ICs), the chip scale package (CSP) and the wafer level package have been invented to meet the requirements for higher input/output pin count, higher heat-dissipating capacity and reduction of the package size. Furthermore, associated packaging techniques for reducing the weight and cost are also being developed.
In the development of the chip scale package (CSP), a variety of techniques such as the single chip package, the stack chip package and the planar multi-chip package (MCM) are developed. The aforementioned techniques can reduce the dimension of a package to a size only slightly larger than the original size of the chip. However, the technology of the stack chip packages and the planar multi-chip packages must be combined with the known good die (KGD) technique to produce a high yield.
Unlike the conventional chip scale package (CSP) method, the waver level package or wafer level chip scale package (WL-CSP) method packages an entire wafer before dicing up the wafer. Hence, the WL-CSP method can eliminate many process steps such as underfilling, assembling, substrate processing, chip attaching and wire bonding so that the overall fabrication cost can be substantially reduced. In general, the wafer can be packaged regardless of the size of the chip or the pin count. In other words, the wafer level packaging is able to reduce the process steps to thereby shorten the fabrication cycle time, to improve the performance and to lower down the cost. In addition, the amount of saving increases correspondingly with the size of the wafer. Therefore, the wafer level packaging method is particularly advantageous to the wafer processing plants shifting from 8-inch wafer production to 12-inch wafer production.
System on chip (SOC) and system in a package (SIP) are regarded as two principal techniques for producing miniaturized and multi-functional semiconductor devices in the future. In particular, the system on chip (SOC) technique has some promising applications in manufacturing digital information products. At present, the multi-chip package modules with high operating frequency, low cost, small size and short fabrication cycle are the dominant packaging type. For example, a drawing chip or a memory chip is often fabricated by the multi-chip package technology to achieve the high processing frequency, super-fast processing speed and the capacity of integration of multi-functions. Therefore, the known good die technique is important in the packaging process of the multi-chip package technology. After a number of chips are packaged, and the electrical properties of each packaged chip is tested. The chips that fail the test are immediately discarded and the chips that pass the test are integrated by attaching to a packaging product. In this way, the area of the printed circuit board of the package system is reduced and the yield of a conventional multi-chip package is increased.